Many electronic devices have components that include an integrated memory. Often, the manufacturer of these devices wants to monitor usage to determine a remaining life of the device. One example of these devices is a printer having a memory on a printing cartridge.
The host device must be able to communicate with the memory in order to receive the information stored in the memory device and to command updating of the information stored in the memory device.
U.S. Pat. No. 7,844,786 discloses addressing and command protocols for addressing an electronic circuit having a non-volatile memory. As shown in FIG. 1, the processing device 101 controls a voltage regulator 102 that provides a voltage source 104 to the memory modules 103a, 103b, . . . 103x that are also provided with a common ground reference 106. The processing device 101 may exchange data with one or more of the non-volatile memory modules 103a, 103b, . . . 103x through an address/data channel 108. The controlling computer system 101 may also provide a common time reference to the memory modules 103a, 103b, . . . 103x through a clock channel 121. A conductor 114 with a set of discrete voltage levels is provided through the use of resistors 118, and where each discrete voltage level corresponds to a particular bit position in the memory module address.
This patent discloses that a busy/available status may be provided on the first channel by effectively “anding” the busy/available output signals from each of the memory modules through the use of an open-collector/open-drain 112. The open-collector/open-drain 112 may include one or more common resistors and one or more capacitors. In such a configuration, each memory module 103a, 103b, . . . 103x may output a high voltage signal if it is able to accept a command, or a low voltage signal if it is busy executing a command. Thus, if all of the memory modules 103a, 103b, . . . 103x are available, then the first channel signal may be pulled up to a “high” voltage by the resistor in the open-collector/open-drain 112, signifying that all of the memory modules 103a, 103b, . . . 103x are available.
This patent also teaches that if any memory module 103a, 103b, . . . 103x is busy, then the first channel signal may be pulled to a “low” voltage close to ground by the open-collector/open-drain 112. If at least one memory module 103a, 103b, . . . 103x is busy, the processing device 101 may wait until the first channel signal is pulled to a high voltage level before issuing a subsequent command to the memory modules 103a, 103b, . . . 103x. In this manner, the processing device 101 may synchronize the memory modules 103a, 103b, . . . 103x before issuing a common command, such as an increment counter command, to a plurality of the memory modules 103a, 103b, . . . 103x. Similarly the second channel may also effectively “and” the error/no-error output signals from each of the memory modules. This may also be provided with another open-collector/open-drain 112 having a common resistor and capacitor.
Each of the memory modules 103a, 103b, . . . 103x may output a high voltage signal on the second channel when there is no error detected and a low voltage signal if an error is detected. Thus, if one of the memory modules 103a, 103b, . . . 103x has an error, the second channel may be pulled to a low voltage by the open-collector/open-drain 112, signifying that at least one memory module 103a, 103b, . . . 103x contains an error. If all of the memory modules 103a, 103b, . . . 103x are error-free, then the second channel may be pulled to a high voltage. All of the memory modules 103a, 103b, . . . 103x will be ready and error-free if the first and second channels are at a high voltage level. It will be appreciated by one of ordinary skill that there are many alternatives to the “anding” function of open-collector/open drain 112 discussed above. For example, a plurality of physical “and” gates can be used instead of the open-collector/open-drain 112.
The status channel 110 may include only a single channel capable of representing the ready, error, and busy states for the memory modules 103a, 103b, . . . 103x. When only a single channel is used, all addressed memory modules 103a, 103b, . . . 103x may release their respective busy signals from a low voltage level to a high voltage level after each finishes processing its current command. The status channel 110 may then be pulled to a high voltage level by the open-drain/open-collector 112. Once the addressed memory modules 103a, 103b, . . . 103x have completed their commands and released each of their output signals above the low voltage, any memory module that needs to report an error may hold the status channel 110 at an intermediate voltage level that is higher than the low voltage level (e.g., close to ground) but lower than the high voltage (e.g., approximately 3.3V). For instance, each of the memory modules 103a, 103b, . . . 103x may use a 1.5V Zener diode component to ground to provide the intermediate voltage level. Other methods of providing an intermediate voltage levels may alternatively be implementing using resistors, as is known in the art, such as using a 5.1 KOhms resistance to ground to provide the intermediate voltage level. In this way, a single status channel 110 may be sufficient for reporting the ready, error, and busy states of the memory modules 103a, 103b, . . . 103x thereby reducing the electrical connections required between the processing device 101 and the memory modules 103a, 103b, . . . 103x. 
A disadvantage of to the above addressing scheme is that it requires additional elements to provide three voltage levels at one channel.